This In modern VLSI systems, Static Random-Access Memory (SRAM) plays a vital role in enhancing on-chip data storage performance. As technology scales down, designing SRAM cells with low power consumption, improved stability, and reduced delay becomes increasingly critical. This project presents the design and analysis of a 10-transistor (10T) SRAM cell operating at low voltage using the Cadence Virtuoso EDA tool with 45nm CMOS technology. The 10T SRAM cell architecture offers improved read and write stability compared to conventional 6T designs, making it highly suitable for sub-threshold and near-threshold operations. In this work, the SRAM cell is analyzed in terms of average and delay during read and write operations under low supply voltage conditions. Simulation results are obtained using transient and parametric analyses to evaluate the cell's performance. The findings demonstrate that the proposed 10T SRAM cell maintains reliable operation with reduced average and delay, offering a promising solution for low-power and high-performance memory applications in advanced integrated circuits. The overall study contributes to the ongoing research in energy-efficient memory design for future nano-scale CMOS technologies
