As FPGA architectures and design scales become more complex, routing becomes the most time-consuming stage in the design process. The efficiency and quality of FPGA routers are challenged by the increasing complexity of connections between logic pins inside CLBs of FPGAs. When creating pathways inside CLBs, current negotiation-based rip-up and reroute approaches will produce a significant number of iterations. In this study, we provide a reliable routing architecture for FPGAs with intricate connections between switch boxes and logic components. In order to efficiently address routing congestion within a CLB tile, we suggest a concurrent intra-CLB rerouting technique. The state-of-the-art VTR 8.0 routing algorithm fails at 4 out of 12 benchmarks, but our framework can achieve 100% routing ability in less wire length and runtime, according to experimental results on modified ISPD2016 benchmarks.
